1. Field of the Invention
The present invention relates to non-volatile memory circuits. In particular, the present invention relates to non-volatile memory circuits that use ferroelectric material for persistent storage.
2. Discussion of the Related Art
Memory circuits using ferroelectric materials (e.g., lead zirconate Titanate (PZT)) have been proposed. One type of such memory circuit is simply a capacitor, such as that ferroelectric capacitor 100 of FIG. 1(c). As shown in FIG. 1(c), ferroelectric capacitor 100 includes a layer of ferroelectric material provided between two capacitor plates represented by electrodes formed between a “plate line” (PL) and a “bit line” (BL), respectively.
Ferroelectric capacitor 100 of FIG. 1(c) may be used in one of two ways: (i) as non-volatile memory cell, or as (ii) a volatile memory cell. FIG. 1(a) illustrates the programmed states of ferroelectric capacitor 100 when used as a non-volatile memory cell. As shown in FIG. 1(a), when used as a non-volatile cell, a high programming voltage (e.g., VPP, where VPP may be 5 v volts, for example) is applied across ferroelectric capacitor 100 to program ferroelectric capacitor 100 into a first phase or programmed state, representing the stored data bit “0”. After the imposed voltage across ferroelectric capacitor 100 is removed, the ferroelectric material in ferroelectric capacitor 100 maintains the programmed “0” state for a long time (e.g., tens of years). Alternatively, ferroelectric capacitor 100 may be programmed into a second phase or programmed state by applying a high negative voltage (e.g., −VPP) across storage capacitor 100, representing the erased data bit “1”. When the imposed voltage across capacitor 100 is removed, the ferroelectric material in storage capacitor 100 maintains the programmed “1” state for a long time (e.g., tens of years).
FIG. 1(b) illustrates the programmed states of ferroelectric capacitor 100 when used as a volatile memory cell. As shown in FIG. 1(b), when used as a volatile cell, a programming voltage (e.g., Vcc e.g., 1 v) that is much lower than the programming voltage for the non-volatile state is applied across ferroelectric capacitor 100 to program ferroelectric capacitor 100 into a first phase or programmed state, representing the volatile data bit “0”. When the imposed voltage across capacitor 100 is removed, the ferroelectric material in storage capacitor 100 maintains the programmed “0” state for a relatively much shorter time period (e.g., seconds) than those of the non-volatile states. Alternatively, ferroelectric capacitor 100 may be programmed into a second phase or programmed state by applying a corresponding negative voltage (−Vcc) across storage capacitor 100, representing the volatile data bit “1”. When the imposed voltage across ferroelectric capacitor 100 is removed, the ferroelectric material in storage capacitor 100 maintains the programmed “1” sate for a relatively shorter period of time (e.g., seconds) than those of the non-volatile states.
The higher programming voltage in non-volatile memory cells operation may reduce the endurance of ferroelectric capacitor 100 and provides relatively slow read and write speeds. The low programming voltage for volatile operations allows greater endurance and higher read and write speeds (e.g., comparable to conventional dynamic random access memory (DRAM) speeds). However, in many applications, as in DRAM, ferroelectric capacitor 100 is required to be refreshed periodically to prevent data loss, albeit at a lesser frequency than conventional DRAMs.
FIG. 2(a) shows a ferroelectric static random access memory (FeSRAM) cell 200, which operate as a non-volatile memory cell. As shown in FIG. 2(a), FeSRAM cell 200 includes a conventional 6-transistor static random access memory (SRAM) cell formed by select transistors 201a and 201b, and cross-coupled inverters formed by transistors 202a, 202b, 203a and 203b. FeSRAM 200 also includes ferroelectric capacitors C0 and C1 respectively connected input terminals 204a and 204b of the cross-coupled inverters and the plate line carrying voltage signal PL. During operation, before FeSRAM cell is powered down, the complementary stored data bits of the SRAM cell held at terminals 204a and 204b are written into ferroelectric capacitors C0 and C1, respectively. When power is restored, the complementary data bits in ferroelectric storage capacitors C0 and C1 are written back into the SRAM cell (i.e., to be held at terminals 204a and 204b again).
FIG. 2(b) shows, when power is restored, voltage signal VPW at the power supply line of the SRAM cell, voltage signal PL on the plate line and voltage signals BT and BC at the input terminals 204a and 204b of the cross-coupled inverters of the SRAM cell. FIG. 2(c) shows, before FeSRAM cell 200 is powered down, voltage signal VPW at the power supply line of the SRAM cell, voltage signal PL on the plate line and voltage signals BT and BC at the input terminals of the cross-coupled inverters of the SRAM cell.
Initially, as shown in FIG. 2(c), voltage signal VPW is at VCC, plate line signal PL is at 0.5 VCC, and voltage signals BT and BC are at VCC and 0 volts, respectively. (Transistors 203a and 202b are conducting, and transistors 203b and 202a are non-conducting). To write these states into ferroelectric capacitors C0 and C1, both voltage signals VPW and PL are brought to programming voltage VPP, thereby bringing the voltage across ferroelectric storage capacitor C1 to VPP, thus writing bit ‘0’ into capacitor C1. After ferroelectric storage capacitor C1 has been written, voltage PL on the plate line is brought to 0 volts, such that the voltage across ferroelectric storage capacitor C0 is brought to −VPP, thereby writing bit ‘1’ into capacitor C0. After ferroelectric storage capacitors C0 and C1 are both written, voltage VPW is also brought to 0 volts (i.e., powered down).
When power is restored, as shown in FIG. 2(b), voltage signal VPW is ramped up to VCC, plate line signal PL is held at 0 volts. The stored voltages in ferroelectric storage capacitors C0 (at bit ‘1’) and C1 (at bit ‘0’) are sufficient to render transistors 203a and 202b conducting, and transistors 203b and 202a non-conducting. Accordingly, the voltage signals BT and BC at terminals 204a and 204b are brought to VCC and 0 volts, respectively. Thus, the SRAM cell is returned to its state prior to the power down. At this point, voltage PL is returned to 0.5 VPP, which is its quiescent state. The subsequent operations of FeSRAM cell 200 are essentially those of a conventional SRAM cell.
As can be seen from the discussion above with respect to FIGS. 1(a) and 1(b), during normal operations, signal transitions at the input terminals of the cross-coupled inverters of the SRAM cells place ferroelectric storage capacitors C0 and C1 into their volatile states, and thus the resulting stored data are not preserved.
As voltage PL has signaling requirements that are different from either the power supply voltage VPW or the ground reference, it requires a separate decoder. The routing requirement also increases the size of FeSRAM cell 200 relative to the size of a corresponding conventional SRAM cell.